Loading…
Attending this event?
9-10 July, 2024
Bangkok, Thailand
View More Details & Registration
Note: The schedule is subject to change.

The Sched app allows you to build your schedule but is not a substitute for your event registration. You must be registered for DPDK Summit APAC to participate in the sessions. If you have not registered but would like to join us, please go to the event registration page to purchase a registration.

This schedule is automatically displayed in Indochina Time – ICT (UTC +7). To see the schedule in your preferred timezone, please select from the drop-down menu to the right, above "Filter by Date."

IMPORTANT NOTE: Timing of sessions and room locations are subject to change.

Simple
Expanded
Grid
By Venue
Tuesday, July 9
 

08:00 GMT+07

Registration & Badge Pick-up
Tuesday July 9, 2024 08:00 - 16:30 GMT+07
Foyer
Tuesday July 9, 2024 08:00 - 16:30 GMT+07
Foyer
  Registration / Breaks / Special Events

09:00 GMT+07

Welcome & Opening Remarks - Thomas Monjalon, Maintainer, NVIDIA
Tuesday July 9, 2024 09:00 - 09:20 GMT+07
Ballroom 1 (Level 7)
Speakers
avatar for Thomas Monjalon

Thomas Monjalon

DPDK Maintainer, NVIDIA
Tuesday July 9, 2024 09:00 - 09:20 GMT+07
Ballroom 1 (Level 7)
  Keynote Sessions

09:25 GMT+07

Introducing UACCE Bus of DPDK - Feng Chengwen, Huawei Technologies Co., Ltd
Tuesday July 9, 2024 09:25 - 09:55 GMT+07
Ballroom 1 (Level 7)
The UACCE (Unified/User-space-access-intended Accelerator Framework) targets to provide Shared Virtual Addressing (SVA) between accelerators and processes. The UACCE bus was integrated in DPDK 24.03, it enables accelerator devices like compressors, cryptos, DMA, and ethernet devices to be seamlessly integrated and registered within DPDK applications. This topic will introduce the UACCE's design philosophy and usage, see if DPDK might evolve to support the SVA path to accelerate more areas.
Speakers
avatar for Feng Chengwen

Feng Chengwen

Software Engineer, Huawei
Four years of experience in DPDK community development; maintainer of dmadev, argparse, UACCE bus, HiSilicon DMA device and DMA performance test tool.
Introducing UACCE bus of DPDK pdf
Tuesday July 9, 2024 09:25 - 09:55 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Enhancements and additions to DPDK libraries, functional or performance-wise

10:00 GMT+07

ZXDH DPU Adapter and It's Application - Lijie Shan & Wang Junlong, ZTE
Tuesday July 9, 2024 10:00 - 10:30 GMT+07
Ballroom 1 (Level 7)
ZTE has introduced a new ASIC-based enhanced data processor product to the DPDK community. This product series incorporates a programmable packet processing pipeline and offers extensive hardware offloading capabilities, including networking, storage, data encryption/decryption, and RDMA support. It also provides driver interfaces for leveraging its hardware capabilities within DPDK/SPDK and other open source communities, facilitating rapid development of services and applications. Its applicability spans across various use cases such as virtualization, AI computing, and security.
Speakers
avatar for wang junlong

wang junlong

software engineer, ZTE Corporation
Software Development Engineer at ZTE Corporation, Nanjing, Engaged in the development of DPDK network software.
avatar for lijie shan

lijie shan

System Engineer, ZTE Corporation
System Engineer
Tuesday July 9, 2024 10:00 - 10:30 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Hardware NIC capabilities and offloads
  • Audience Experience Level Any

10:30 GMT+07

Coffee Break
Tuesday July 9, 2024 10:30 - 11:00 GMT+07
Zeta Cafe (Level 8)
- All Day Coffee/Decaf/Tea
- All Day Water
- Sugar + Sugar Substitutes
- Milk + Milk Alternatives

- Green Godness Sandwich (Gluten free, VEG)
- Chicken Sausage
- Assorted Swiss roll
- Fruit Platter (Gluten free)
Tuesday July 9, 2024 10:30 - 11:00 GMT+07
Zeta Cafe (Level 8)
  Registration / Breaks / Special Events

11:00 GMT+07

Libtpa Introduction - Yuanhan Liu, Bytedance
Tuesday July 9, 2024 11:00 - 11:50 GMT+07
Ballroom 1 (Level 7)
This presentation introduces Libtpa, yet another open source DPDK based userspace TCP stack implementation. What distinguishes Libtpa from many other userspace TCP stacks is its ability to coexist natively with the Linux kernel networking stack. Libtpa is highly efficient, capable of boosting the Redis performance by upto 5 times. Moreover, Libtpa is sort of stable, backed by more than 200 unit tests. In addition, Libtpa offers a rich set of debug tools, among which the sock tracing is particularly handy on debugging.
Speakers
avatar for Yuanhan Liu

Yuanhan Liu

Software Engineer, ByteDance
Software Engineer at ByteDance
Tuesday July 9, 2024 11:00 - 11:50 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, New networking technologies and their applicability to DPDK

11:55 GMT+07

Telecom Packet Processing and Correlation Engine Using DPDK - Ilan Raman, Aviz Networks
Tuesday July 9, 2024 11:55 - 12:25 GMT+07
Ballroom 1 (Level 7)
The exponential growth in telecommunications users has led to significantly increased bandwidth requirements. As a result, telecom operators are seeking solutions to develop software-based, scalable packet processing products. This proposal explores the utiliisation of DPDK capabilities to build high-speed, line-rate telecom packet processing systems. These systems enable metadata extraction from control and user plane packets and achieve control-user correlation using DPDK hash algorithms. It provides the packet processing libraries to extract the protocol packets from different interfaces like N11, N4, N3, S1-U, S11 etc. And the packets from these different interfaces require the packet stripping, adjustment, modifications to extract the necessary data which is achieved using DPDK MBUF Packet processing library APIs. The proposal can scale to multiple cores per port using the efficient RSS load-balancing techniques offered in NiC using DPDK Flow modules. The modular and robust DPDK library APIs allow building such Packet processing systems in a very short span of delivery time with high efficiency and quality.
Speakers
avatar for Ilan Raman

Ilan Raman

Software Technical Lead, Aviz Networks
Myself Ilan working with Aviz Networks. Currently involved in building high performance scalable software based packet processing engines for various telco use cases using DPDK.
Tuesday July 9, 2024 11:55 - 12:25 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, New networking technologies and their applicability to DPDK

12:30 GMT+07

Lunch Break
Tuesday July 9, 2024 12:30 - 14:00 GMT+07
Zeta Cafe (Level 8)
- Seafood on ice/ Gluten Free
- Assorted Sushi
- Spicy Minced Chicken Salad
- Seafoods Glass Noodle Salad / Gluten Free
- Greek Salad / Gluten Free, VEG
- Potato Salad
- Tom Yum Kung (Shrimp Spicy and Sour Soup)
- Pumpkin Soup / Gluten Free, VEG
- Rice / Gluten Free
- Egg Fried Rice / Gluten Free
- Stir Fried Spicy Pork with Basil
- Orange Chicken (Sweet and Sour Chicken) / Gluten Free
- Bake Potatoes / Gluten Free, VEG
- Steamed Fish with Lime and Chillies / Gluten Free
- Steamed Rice Top with Chicken
- Pasta Penne Alfredo

- Black and White Chocolate Mousse
- Carrot Cake
- Cheesecake
- Mango Mousse
- Red Velvet Cake
- Chocolate Brownie Cake // Vegan (Non-diary)
- Green Tea brownie Cake
- Jam Roll
- Custard Caramel
- Panacotta / Gluten Free
Tuesday July 9, 2024 12:30 - 14:00 GMT+07
Zeta Cafe (Level 8)
  Registration / Breaks / Special Events

14:00 GMT+07

Cryptodev and Security Library Updates in DPDK - Akhil Goyal & Anoob Joseph, Marvell
Tuesday July 9, 2024 14:00 - 14:40 GMT+07
Ballroom 1 (Level 7)
In the past few releases of DPDK, there has been an addition of various protocol offloads and useful features in rte_security which are not much explored and needs to be highlighted. - MACsec - Provides point-to-point security on Ethernet(Layer 2) links. - TLS/DTLS record protocol - A layer 4 security protocol - Rx flow inject - An alternate datapath for security processing in cases when the inline protocol processing cannot be performed due to non-protocol reasons like outer fragmentation etc. - IPv4/IPv6 reassembly on inline inbound IPsec processing. New algorithms added in cryptodev - ShangMi algorithms - SM2/SM3/SM4 - Secure Hash Algorithm and KECCAK (SHAKE) - Updates on asymmetric crypto This session will explain the details about the offloads and their corresponding use cases along with future roadmap for cryptodev and security libraries.
Speakers
avatar for Akhil Goyal

Akhil Goyal

Senior Staff Engineer, Marvell Semiconductors
I work as Principal Engineer at Marvell, member of its Dataplane and Accelarators team. I mainly contribute to the DPDK project, for which working as maintainer for dpdk-next-crypto tree. I have made significant contributions to rte_security, IPsec, PDCP, MACsec, and various Crypto... Read More →
avatar for Anoob Joseph

Anoob Joseph

Senior Principal Engineer, Marvell Semiconductors
I lead the crypto & security protocols team at Marvell. With close to 7 years of contributions in DPDK, I've been involved in enhancing support for network security protocols in DPDK. I had introduced hardware acceleration for protocols such as IPsec & TLS via rte_security and introduced... Read More →
Tuesday July 9, 2024 14:00 - 14:40 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Enhancements and additions to DPDK libraries, functional or performance-wise

14:45 GMT+07

Unified Representor with Large Scale Ports - Suanming Mou, NVIDIA Semiconductor
Tuesday July 9, 2024 14:45 - 15:15 GMT+07
Ballroom 1 (Level 7)
In switchdev mode, the DPDK application manages the proxy (PF) port and VF/SF by using representors. When a packet has no matching rule in HW, it is considered a miss packet and will be sent to the port representor that matches the origin port of the packet. With HW advancements supporting hundreds of VMs and frameworks like Kubernetes that can scale to thousands of pods, the number of ports has increased significantly. The model where each VF/SF port is managed by a corresponding software representor can no longer handle such demand effectively. It consumes a lot of memory, and the software poll all ports, wasting cycles on empty queues, and causing cache misses. It also takes a long time to initialize and set up. RTE_ETH_DEV_CAPA_RXQ_SHARE was introduced earlier to mitigate this issue, but users still need to configure and setup the queues per port. The new model allows a user to configure the Rx/Tx queue on a proxy port and manage all pkts through the proxy port’s Rx/Tx queue and a single switch representor for handling miss traffic. This approach solves the scaling issue, allowing the management of thousands of ports effectively and using CPU cycles much more efficiently.
Speakers
avatar for Suanming Mou

Suanming Mou

Sr. Engineer, NVIDIA Semiconductor Shanghai
Linux network and system kernel engineer with over ten years of experience.
Tuesday July 9, 2024 14:45 - 15:15 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Hardware NIC capabilities and offloads
  • Audience Experience Level Any

15:15 GMT+07

Coffee Break
Tuesday July 9, 2024 15:15 - 15:45 GMT+07
Zeta Cafe (Level 8)
- All Day Coffee/Decaf/Tea
- All Day Water
- Sugar + Sugar Substitutes
- Milk + Milk Alternatives

- Grilled Cucumber & Tomato Sandwich, Basalmic reduction (Gluten free, VEG)
- Chocolate marble cake
- Fruit Platter (Gluten free)
- Chocolate chip Cookies
Tuesday July 9, 2024 15:15 - 15:45 GMT+07
Zeta Cafe (Level 8)
  Registration / Breaks / Special Events

15:45 GMT+07

Troubleshooting Low Latency Application on CNF Deployment - Vipin Varghese & Sivaprasad Tummala, AMD India Pvt Ltd
Tuesday July 9, 2024 15:45 - 16:15 GMT+07
Ballroom 1 (Level 7)
Share & enlighten on the challenges, hiccups to address DPDK application targeted for low latency (Virtual RAN and Packet core) in a container environment.
Speakers
avatar for Sivaprasad Tummala

Sivaprasad Tummala

Technical Staff Engineer, AMD India Pvt Ltd
Solutions Architect and Performance Tuning expert for High speed packet processing applications and accelerate Network transformation, performance tuning and Power Efficient Compute for Network and Storage workloads on x86 COTS, Accelerators for Crypto/Compression/Baseband, Storage... Read More →
avatar for Vipin Varghese

Vipin Varghese

Senior Member of Technical Staff SW Developer, AMD
Diversified experience in Network Application Acceleration with a focus on analysis, performance tuning, and architecting solutions using technologies such as DPDK (x86), Ezchip (NP4, NP5), Tilera (8036, 8072) on Linux for user and kernel. Keen interest in building solutions using... Read More →
Tuesday July 9, 2024 15:45 - 16:15 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Developer stories, technical challenges when integrating or developing with DPDK

16:20 GMT+07

Suggestions to Enhance DPDK to Enable Migration of User Space Networking Applications to DPDK - Vivek Gupta, Benison Technologies Pvt Ltd
Tuesday July 9, 2024 16:20 - 16:50 GMT+07
Ballroom 1 (Level 7)
Currently, there are quite a few challenges in migrating the various open-source applications to DPDK to achieve higher throughputs. The talk discusses some suggestions to enhance DPDK library to enable easier migration to achieve higher throughputs.
Speakers
avatar for Vivek Gupta

Vivek Gupta

C.T.O., Benison Technologies Private Limited
Have been working on different Datapath applications using VPP, DPDK, Linux Kernel. Delivering solutions to the customers in various Networking, Network Security, End Point Security spaces
Tuesday July 9, 2024 16:20 - 16:50 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Enhancements and additions to DPDK libraries, functional or performance-wise
  • Audience Experience Level Any

16:55 GMT+07

Closing Remarks - Jerin Jacob, Senior Director, Marvell
Tuesday July 9, 2024 16:55 - 17:05 GMT+07
Ballroom 1 (Level 7)
Speakers
avatar for Jerin Jacob

Jerin Jacob

Senior Director, Marvell
I am part of DPDK tech board. Also maintaining next-event and next-net-mrvl DPDK tree. I am also responsible for maintaining Trace, Graph, Eventdev subsystem in DPDK. I work for Marvell.
Tuesday July 9, 2024 16:55 - 17:05 GMT+07
Ballroom 1 (Level 7)
  Keynote Sessions

18:00 GMT+07

All Attendee Networking Reception 🎉
Tuesday July 9, 2024 18:00 - 22:00 GMT+07
Medinii Restaurant
Come mix and mingle with your fellow attendees! 
Tuesday July 9, 2024 18:00 - 22:00 GMT+07
Medinii Restaurant 35th Floor 413 Sukhumvit Klongtoey Nua Khlong Toei Nuea, Watthana, Bangkok 10110, Thailand
  Registration / Breaks / Special Events
 
Wednesday, July 10
 

08:00 GMT+07

Registration & Badge Pick-up
Wednesday July 10, 2024 08:00 - 16:30 GMT+07
Foyer
Wednesday July 10, 2024 08:00 - 16:30 GMT+07
Foyer
  Registration / Breaks / Special Events

09:00 GMT+07

Welcome Back - Prasun Kapoor, Associate Vice President, Marvell
Wednesday July 10, 2024 09:00 - 09:05 GMT+07
Ballroom 1 (Level 7)
Speakers
PK

Prasun Kapoor

Associate Vice President, Marvell Technologies
Wednesday July 10, 2024 09:00 - 09:05 GMT+07
Ballroom 1 (Level 7)
  Keynote Sessions

09:10 GMT+07

PDCP Packet Processing Library in DPDK - Libpdcp - Anoob Joseph & Akhil Goyal, Marvell
Wednesday July 10, 2024 09:10 - 09:50 GMT+07
Ballroom 1 (Level 7)
PDCP is a protocol that plays a crucial role in the UMTS, LTE and 5G air interfaces. In radio protocol stack, PDCP sits above the RLC (Radio Link Control) layer and below the RRC or user plane upper layers (like IP at the UE). PDCP handles the transfer of both user plane and control plane data. PDCP ensures security of the data transmitted by using ciphering and integrity protection. It has additional features such as in-order delivery, duplicate discard, windowing based anti-replay protection, timer based SDU discard etc. PDCP protocol relies on features that are implemented in DPDK by various libraries such as 1. rte_reorder - in-order delivery, duplicate discards 2. rte_cryptodev & rte_security - ciphering, integrity protection 3. rte_timer & rte_event - timers for SDU discard, reordering Lib PDCP provide a standard abstraction to PDCP datapath processing. The library implements all protocol specific handling with portions of protocol offloaded to rte_cryptodev based on its capability. This session would introduce the protocol, explain changes added in other libraries to adapt it for PDCP use case and generic walkthrough of PDCP library from application usage perspective.
Speakers
avatar for Akhil Goyal

Akhil Goyal

Senior Staff Engineer, Marvell Semiconductors
I work as Principal Engineer at Marvell, member of its Dataplane and Accelarators team. I mainly contribute to the DPDK project, for which working as maintainer for dpdk-next-crypto tree. I have made significant contributions to rte_security, IPsec, PDCP, MACsec, and various Crypto... Read More →
avatar for Anoob Joseph

Anoob Joseph

Senior Principal Engineer, Marvell Semiconductors
I lead the crypto & security protocols team at Marvell. With close to 7 years of contributions in DPDK, I've been involved in enhancing support for network security protocols in DPDK. I had introduced hardware acceleration for protocols such as IPsec & TLS via rte_security and introduced... Read More →
Wednesday July 10, 2024 09:10 - 09:50 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Enhancements and additions to DPDK libraries, functional or performance-wise
  • Audience Experience Level Any

09:55 GMT+07

Coupling Eventdev Usage with Traffic Metering & Policing (QoS) - Sachin Saxena & Apeksha Gupta, NXP
Wednesday July 10, 2024 09:55 - 10:25 GMT+07
Ballroom 1 (Level 7)
There was a customer requirement to have Rx scheduling for incoming packets after applying metering and policing traffic management based on RFC-2698. The use case requires only one thread (lcore) to dequeue packets and packets should be received in priority order (highest priority first). NXP has all these 3 features in DPAA2 H/W and we extended eventdev framework usage to integrate H/W RX Scheduler with H/W based Metering & Policing module.
Speakers
avatar for Apeksha Gupta

Apeksha Gupta

Software Engineer, NXP
Software Engineer (4+ years) with experience in various projects-platform software developement in DPDK. Major work done area is on i.MX & DPAA2 platforms.
avatar for Sachin Saxena

Sachin Saxena

Lead Software Engineer, NXP
Working with Freescale/NXP from 10 years as Networking application developer and expertise in datapath performance optimization. Working exp on DPDK, ODP, VPP odp-vpp(Linaro project) etc.
Wednesday July 10, 2024 09:55 - 10:25 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Hardware NIC capabilities and offloads
  • Audience Experience Level Any

10:25 GMT+07

Coffee Break
Wednesday July 10, 2024 10:25 - 10:55 GMT+07
Zeta Cafe (Level 8)
- All Day Coffee/Decaf/Tea
- All Day Water
- Sugar + Sugar Substitutes
- Milk + Milk Alternatives

- Cucumber Hummus sandwich (Gluten free, VEG)
- Rainbow cake Cake Custard
- Fruit Platter (Gluten Free)
- Oatmeal Cookies
Wednesday July 10, 2024 10:25 - 10:55 GMT+07
Zeta Cafe (Level 8)
  Registration / Breaks / Special Events

10:55 GMT+07

Re-Imagining GRO - Kumara Parameshwaran Rathinavel, Microsoft
Wednesday July 10, 2024 10:55 - 11:25 GMT+07
Ballroom 1 (Level 7)
The current GRO library in DPDK is suboptimal. For every packet, to verify the presence of the current 5-tuple in the GRO table, a lookup is performed on each flow. Implementing a hash-based solution for the 5-tuple would be an efficient optimization. Furthermore, it would be advantageous if applications could configure the timeout for a specific flow or 5-tuple. The existing timer mode in GRO applies a static timeout for any application, which is not ideal. The timeout should be adjustable based on the latency sensitivity of the application. If the GRO layer processes flows from different applications, a single timeout setting could lead to suboptimal performance for others. Providing an infrastructure within GRO for applications to set timeouts for tuples would be beneficial. This would allow for the judicious use of GRO resources, optimizing for different types of traffic, such as mice versus elephant flows. If packets from multiple applications are processed by the GRO layer, the varying latency tolerances could be accommodated by setting appropriate GRO timeouts.
Speakers
avatar for Kumara Parameshwaran Rathinavel

Kumara Parameshwaran Rathinavel

Senior Software Engineer, Microsoft
Myself Param, I have been working for almost close to 10 years. I am working with Microsoft as Senior Software Engineer. For the past 5+ years I have been actively using DPDK. In DPDK I have contributed in fixing bugs in GRO layer and also added GRO support for IPv6. My contributions... Read More →
Wednesday July 10, 2024 10:55 - 11:25 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Enhancements and additions to DPDK libraries, functional or performance-wise
  • Audience Experience Level Any

11:30 GMT+07

Refactor Power Library for Vendor Agnostic Uncore APIs - Sivaprasad Tummala & Vipin Varghese, AMD India Pvt Ltd
Wednesday July 10, 2024 11:30 - 11:50 GMT+07
Ballroom 1 (Level 7)
Refactor power management library to introduce Uncore APIs. This facilitates seamless integration of various vendor uncore implementations.
Speakers
avatar for Sivaprasad Tummala

Sivaprasad Tummala

Technical Staff Engineer, AMD India Pvt Ltd
Solutions Architect and Performance Tuning expert for High speed packet processing applications and accelerate Network transformation, performance tuning and Power Efficient Compute for Network and Storage workloads on x86 COTS, Accelerators for Crypto/Compression/Baseband, Storage... Read More →
avatar for Vipin Varghese

Vipin Varghese

Senior Member of Technical Staff SW Developer, AMD
Diversified experience in Network Application Acceleration with a focus on analysis, performance tuning, and architecting solutions using technologies such as DPDK (x86), Ezchip (NP4, NP5), Tilera (8036, 8072) on Linux for user and kernel. Keen interest in building solutions using... Read More →
Wednesday July 10, 2024 11:30 - 11:50 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Enhancements and additions to DPDK libraries, functional or performance-wise

11:55 GMT+07

Q&A with the Governing Board & Technical Board
Wednesday July 10, 2024 11:55 - 12:15 GMT+07
Ballroom 1 (Level 7)
Governing Board
  • Wang Yong (ZTE)
Technical Board
  • Thomas Monjalon (Mellanox/NVIDIA) – Lead Maintainer
  • Jerin Jacob (Marvell)
Speakers
WY

Wang Yong

Senior Software Engineer, ZTE
I am a sofeware engineer of ZTE corporation. I have been worked in developing fast datapath software with DPDK for 4years and with VPP for 2years.
avatar for Thomas Monjalon

Thomas Monjalon

DPDK Maintainer, NVIDIA
avatar for Jerin Jacob

Jerin Jacob

Senior Director, Marvell
I am part of DPDK tech board. Also maintaining next-event and next-net-mrvl DPDK tree. I am also responsible for maintaining Trace, Graph, Eventdev subsystem in DPDK. I work for Marvell.
Wednesday July 10, 2024 11:55 - 12:15 GMT+07
Ballroom 1 (Level 7)
  Breakout Session

12:15 GMT+07

Lunch Break
Wednesday July 10, 2024 12:15 - 13:45 GMT+07
Zeta Cafe (Level 8)
- Seafood on ice/ Gluten Free
- Assorted Sushi
- Pork Glass Noodle Salad
- Spicy Grilled Chicken Salad
- Cucumber Salad / VEG
- Hawaiian Salad
- Pork Spicy and Sour Soup with Tamarind Leaves
- Carrot Soup / Gluten Free, VEG
- Rice / Gluten Free
- Dark Soy Fried Rice
- Red Curry with Chicken
- Roasted Pork Orange Sauce/ Gluten Free
- Carrot with Honey / Gluten Free, VEG
- Steamed Fish with Lime and Chillies
- Rice Noodle with Fish Curry
- Pasta Spaghetti garlic chilli / VEG

- Orange Cake
- Lemon Tart
- Taro Cake
- Green Tea Chocolate Brownie
- Blueberry Cheese Cake
- Mango Mousse
- Coconut Pudding / Vegan,Gluten free
- Lamington
- Panacotta / Gluten free
- Strawberry Tart
Wednesday July 10, 2024 12:15 - 13:45 GMT+07
Zeta Cafe (Level 8)
  Registration / Breaks / Special Events

13:45 GMT+07

Rte_flow Match with Comparison Result - Suanming Mou, NVIDIA Semiconductor
Wednesday July 10, 2024 13:45 - 14:05 GMT+07
Ballroom 1 (Level 7)
Exact or wildcard matches are the two traditional match methods in DPDK rte_flow. These methods involve either matching specific values in packet headers (e.g., IP addresses, ports) or ignoring specific fields while matching others. But if a user wants to match packets with TCP port above a specific value, this is not supported with these two match methods. In this session, we will introduce the newly added RTE_FLOW_ITEM_TYPE_COMPARE item, which addresses the limitations of traditional match methods by providing advanced and flexible matching capabilities. It supports match with various comparative operation results, such as equal to, less than, less than or equal to, greater than, greater than or equal to, and not equal to. This enables range and conditional matching, allowing for more precise traffic management. For example, it can match packets with field values exceeding a certain threshold.
Speakers
avatar for Suanming Mou

Suanming Mou

Sr. Engineer, NVIDIA Semiconductor Shanghai
Linux network and system kernel engineer with over ten years of experience.
Wednesday July 10, 2024 13:45 - 14:05 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Hardware NIC capabilities and offloads
  • Audience Experience Level Any

14:10 GMT+07

DPDK PMD Live Upgrade - Rongwei Liu, Nvidia
Wednesday July 10, 2024 14:10 - 14:40 GMT+07
Ballroom 1 (Level 7)
When a DPDK application must be upgraded, the traffic downtime should be shortened as much as possible. During the migration time, the old application may stay alive while the new one starts and is configured. To optimize the switch to the new application, the old application may need to be aware of the presence of the new application being prepared. This is achieved with a new API allowing the user to change the new application state to standby and active later.
Speakers
avatar for Rongwei Liu

Rongwei Liu

Software engineer, NVIDIA
I am from Nvidia and focus on the networking technology. At Nvidia, my major experience is on the hardware offload, PMD functionality, etc.
Wednesday July 10, 2024 14:10 - 14:40 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Hardware NIC capabilities and offloads

14:40 GMT+07

Coffee Break
Wednesday July 10, 2024 14:40 - 15:10 GMT+07
Zeta Cafe (Level 8)
- All Day Coffee/Decaf/Tea
- All Day Water
- Sugar + Sugar Substitutes
- Milk + Milk Alternatives

- Club Sandwich (Gluten free)
- Vegetable Pizza (VEG)
- Scones with Jam & Clotted Cream (Non Gluten)
- Fruit Platter (Gluten Free)
Wednesday July 10, 2024 14:40 - 15:10 GMT+07
Zeta Cafe (Level 8)
  Registration / Breaks / Special Events

15:10 GMT+07

Monitoring 400G Traffic in DPDK Using FPGA-Based SmartNIC with RTE Flow - David Vodák, Cesnet
Wednesday July 10, 2024 15:10 - 15:40 GMT+07
Ballroom 1 (Level 7)
As 400G wire speed becomes more widely adopted, the need to monitor traffic at 400G is growing daily. DPDK can be a great help to achieve this speed as it provides excellent throughput results. However, monitoring packets at 400G can be challenging, so hardware acceleration also comes in handy. FPGA chips are a suitable option because they can be programmed to perform hardware offload and are powerful enough to support the processing pipeline even at 400G. Developers at CESNET have designed the first 400G FPGA-based SmartNIC that supports DPDK. It contains the Intel Agilex 7 FPGA, which provides enough resources to implement a processing pipeline. This pipeline is able to mark and filter packets and much more at 400 Gbps. It can be configured via RTE flow to help accelerate monitoring as well as many other tasks.
Speakers
avatar for David Vodák

David Vodák

Software Engineer, Cesnet
He has graduated from the Brno University of Technology three years ago. His bachelor's and master's thesis were focused on developing RTE flow support for OvS acceleration on cards COMBO (PMD nfb) and Intel Pac N3000 (PMD ipn3ke). He used to develop DPDK-based DDOS mitigation application... Read More →
Wednesday July 10, 2024 15:10 - 15:40 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Developer stories, technical challenges when integrating or developing with DPDK

15:45 GMT+07

Lessons Learnt from Reusing QDMA NIC to Base Band PMD - Vipin Varghese & Sivaprasad Tummala, AMD India Pvt Ltd
Wednesday July 10, 2024 15:45 - 16:15 GMT+07
Ballroom 1 (Level 7)
Share learnings and findings converting AMD Xilinx FPGA from NIC PMD to BBDEV PMD. 
Speakers
avatar for Sivaprasad Tummala

Sivaprasad Tummala

Technical Staff Engineer, AMD India Pvt Ltd
Solutions Architect and Performance Tuning expert for High speed packet processing applications and accelerate Network transformation, performance tuning and Power Efficient Compute for Network and Storage workloads on x86 COTS, Accelerators for Crypto/Compression/Baseband, Storage... Read More →
avatar for Vipin Varghese

Vipin Varghese

Senior Member of Technical Staff SW Developer, AMD
Diversified experience in Network Application Acceleration with a focus on analysis, performance tuning, and architecting solutions using technologies such as DPDK (x86), Ezchip (NP4, NP5), Tilera (8036, 8072) on Linux for user and kernel. Keen interest in building solutions using... Read More →
Wednesday July 10, 2024 15:45 - 16:15 GMT+07
Ballroom 1 (Level 7)
  Breakout Session, Enhancements and additions to DPDK libraries, functional or performance-wise

16:20 GMT+07

Closing Remarks - Nathan Southern, Sr. Projects Coordinator, The Linux Foundation
Wednesday July 10, 2024 16:20 - 16:25 GMT+07
Ballroom 1 (Level 7)
Speakers
avatar for Nathan Southern

Nathan Southern

Project Coordinator, The Linux Foundation
Wednesday July 10, 2024 16:20 - 16:25 GMT+07
Ballroom 1 (Level 7)
  Keynote Sessions
 
  • Filter By Date
    Jul 9 -10, 2024
  • Filter By Venue
    Bangkok, Thailand
    All
    Ballroom 1 (Level 7)
    Foyer
    Medinii Restaurant
    Zeta Cafe (Level 8)
  • Filter By Type
    Breakout Session
    All
    Developer stories
    Enhancements and additions to DPDK libraries
    Hardware NIC capabilities and offloads
    New networking technologies and their applicability to DPDK
    functional or performance-wise
    technical challenges when integrating or developing with DPDK
    Keynote Sessions
    Registration / Breaks / Special Events
  • Audience Experience Level
    Any
    Beginner
    Intermediate
  • Timezone
Share Modal

Share this link via

Or copy link

Filter sessions
Apply filters to sessions.
Tuesday, July 9
Wednesday, July 10
Ballroom 1 (Level 7)
Foyer
Medinii Restaurant
Zeta Cafe (Level 8)
  • Breakout Session
  • Keynote Sessions
  • Registration / Breaks / Special Events
  • Audience Experience Level
  • Any
  • Beginner
  • Intermediate